(1) A PDK/CAD/IP infrastructureis essential to company's long term competency. It should be a sincerepart of company's roadmap and strategy. There is not a successfulelectronics design company without a clear, solid, quality andconsistentPDK/EDA/IP infrastructure in place.
(2) Company gains competence by avoidingmistakes and producing NEEDED, VALUE and QUALITY products in time forcustomers. Successful companies avoid and learned from previous orother company's mistakes. While ordinary companies consistently makemistakes! This also true for all nations, political parties andindividuals.
(3) A successful product design is a resultof excellent TEAM executions and GROUP effort. This is particularlytruefor fast track and high risk product design. Not any single person orgroup can claim the ownership for the success. It is to everyteam members' best interest to foster a fair, encouraging,innovative, andrewardingcorporate culture.
(4) In today's globalenvironment, mostparties companies dealing with are smart and knowledgeable.High quality products have their market segment. Value products alsohave their market segment. However, less and less market segments arefor poor electronics. Companies need to push quality,valuable and affordable products as fast as company can. If there aremajor defects or issues in final products, sooner or later customerswill find out and companies will be on Newspaper front pages!
(5) It is always better to catch allerrorsat early stage than late in design and product cycle. It is always costmore tocorrect design mistakes at very last product stage. Products recallseven damage a company'scorporate image.
(6) If a failure mode is already reportedin design or test, then a check for that failure mode should beincorporated into PDK/CAD or design/system validation. Learning byfailure is a costly andsometime not necessary process.
(7) The Quality of the final product is asgoodas your initial design goal, design process and its verification. It isalmost impossibleto design a complete high speed and high performance SOC using anobsolete EDA system. This is just like you can not use a design systemfor motorcycle to design a space shuttle. That is going to be a designdisaster!
(8) Bad or incorrect simulation model leadstofail chip or un-necessary failure debugging. Wrong or incorrect designspecification leads to product mis-function. Wrong or misleading marketprediction lead to complete waste of development resource andother opportunity cost.
(9) Quality PDK deck can catchlayout related mistakes. Carefully review DRC/ERC and LVS resultare essential for first PG success. Also using automation can helphuman to do more, however also need to apply common sense in allsituation. Blindly trustsimulation or verification without double checking is dangerous tofinal qualification of products.
|What is a PDK||A Process Design Kit(PDK) is a processspecific bundled elements to work with the Cadence Custom IC tools.Design and layout engineers use PDK elements to design andcreateanalog mixed/signal integrated circuits.|
A PDK includes Cadence process technology file, PV rule files (LVS,DRC, ERC), Parasitic Extraction (RCX/PEX) andSpice Models, device symbols, component CDF, Skill callbacks,Pcells, etc. Everything you need to do IC designs.
|Physical Verification||All tools or software todo DRC, ERC, LVS, and PEX/RCX check arecalled physical verification..|
|Functional Verification||Functional verificationis the task of verifying the logicdesign conforms to design specification|
Useof various types of logic and mathematical methods to verify thecorrectness of IC logic or system interactions.In otherwords, it attempts to prove or verify that certainrequirements (also expressed formally) aremet, or that certain undesired behaviors (such as deadlock) cannotoccur.
Equivalence checking is the most common formal verification method,which is used to compare the design that is being created against adesign that is already proved accurate.
|Static Timing Analysis||StaticTiming Analysis (STA) is a method of computing the expected timing of adigital circuit without requiring simulation.|
|Hold time violation||A hold time violation,when an input signal change tooquickly, afterthe clock's active transition |
|Setup time violation||A setup time violation,when a signal arrives too late, and misses the time when it shouldadvance|
Scan chains are atechnique used in Design For Test. The objective is to make testingeasier by providing a simple way to set and observe every flip-flop inan IC. A special signal called scanenable is added to a design.When this signal is asserted, every flip-flop in the design isconnected into a long shift register, one input pin provides the datato this chain, and one output pin is connected to the output of thechain. Then using the chip's clock signal, an arbitrary pattern can beentered into the chain of flips flops, and/or the state of every flipflop can be read out.
|Tcl||Tool command language(Tcl) for scripting or GUI|
|Standard VCD||VCD files containsimulation events represented using 4states: 0, 1, X and Z. This format is excellent for capturing vectors. Ability to write out multiple VCD files.|
|Extended VCD||Based on the StandardVCD files by providing additionalinformation in an 8-state format.|
|Code Coverage||Quickly identify holesin the testing process and reducesimulation times. Ability to merge results of multiple option coverageruns and remove or add files from the coverage statistics|
FiniteState Machine (FSM).
An electronic circuit that has a predictable or finite state that isbased on a combination of the circuit's previous state and thecircuit's current set of inputs.
|LSF||Load SharingFacility (LSF)|
|Slack Time||The slack associatedwith each connection is the differencebetween the required time and the arrival time. A positive slack S at anode implies that the arrival time at that node may be increased by Swithout affecting the overall delay of the circuit. Conversely,negative slack implies that a path is too slow, and the path must besped up (or the reference signal delayed) if the whole circuit is towork at the desired speed.|
|STAis a method of computing the expected timing of a digital circuitwithout requiring simulation.|
ReuseMethodology Manual. A set of guidelines that define goodcoding styles for HDL design.
RegisterTransfer Level, the point where the design is written as a registertransfer description. A register transfer description is a type of abehavioral description which is closely related to the hardwareimplementation. The description is written in terms of register banksand combinational logic.
Asoftware tool that performs a predefined set of fixed checks on acoding language such as Verilog, VHDL, C or C++.
JointTest Access Group
Aconsortium of individuals from North American companies whose objectiveis to tackle the challenges of testing high density IC devices.
HardwareDescription Language, a programming language like way of describinghardware. The two most common HDL's are Verilog and VHDL.
|The Accellera FormalVerification Technical Committee has been created to develop andpromote a property specification language compatible with Verilog(IEEE-1364) and VHDL (IEEE-1076). Visit: www.accellera.org for furtherinformation.|
Busfunctional models, a piece of software designed to mimic the behaviorof a hardware interface device.
|PCD||Process Control Document|
|PCM||Process Control Module|
|SCM||Scribeline Control Module|
|LAMP||LAMP is an acronym for asolution stack of free, open sourcesoftware, originally coined from the first letters of Linux(operating system), ApacheHTTP Server, MySQL(database software) and Perl/PHP/Python,principalcomponents to build aviable general purpose web server.|
|TLM||Transaction-levelmodeling (TLM) baseddesign andverification in advanced ICtechnology.|
|OVM||The OpenVerification Methodology (OVM)is the result of joint development between Cadence and Mentor Graphicsto facilitate true SystemVerilog interoperability with a standardlibrary and a proven methodology. Completely open, it combines the bestof the Cadence® Incisive® Plan-to-Closure UniversalReuse Methodology (URM) and the Mentor Advanced VerificationMethodology (AVM), and is usable on two-thirds of the world'sSystemVerilog simulators. The OVM will also facilitate the developmentand usage of plug-and-play verification IP (VIP) written inSystemVerilog (IEEE 1800), SystemC® (IEEE 1666), and e(IEEE 1647) languages. On 18 December 2009, OVM 2.1 wasreleased to OVMWorld.|
|LEC||LEC is nothing but LogicEquivalence checking. LEC can be done with Conformal, Formality, FormalPRo tools. It is basically checking functionality between RTL andNetlist. |
You can check the functionality between pre-layout netlist and postlayout netlist just to make sure that Place & Route tool didn'tmess up anything.
|UPF||UnifiedPower Format, Quick reference,current version is 1.0|
|CPF||Common Power Format, QuickReference, Example coding|
|IBIS||I/O Buffer InformationSpecification|
|SDF||Standard Delay Format(SDF) 1.0, 2.0, 3.0, 4.0|
|SPEF|| Standard ParasiticExchange Format (SPEF) is an IEEEstandard for representing parasitic data of wires in a chip in ASCIIformat. SPEF is most popular specification for parasiticexchangebetween different tools of EDA domain during any phase of design. |
SPEF is an Open Verilog Initiatve (OVI)--and now IEEE--format fordefining netlist parasitics. SPEF is NOT identical to the SPF format,although it is used in a similar manner. Like the SPF format, SPEFincludes resistance and capacitance parasitics. Also like the SPFformat, SPEF can represent parasitic in detailed or reduced (pi-model)forms, with the reduced form probably being more commonly used. SPEFalso has a syntax that allows the modeling of capacitance betweendifferent nets, so it is used by the PrimeTime SI (crosstalk) analysistool. SPEF is smaller than SPF and DSPF because the names are mapped tointegers to reduce file size.
TheDifference Between Parasitic Data Formats SPF, DSPF, RSPF, SPEF, andSBPF
|DSPF||DetailedStandard Parasitic Format(DSPF) is a very different format,meant to be useful in a SPICE simulation. For example, NET sections donot have endings, and comments should start with two asterisks. |
DSPF models a detailed network of RC parasitics for every net. DSPF istherefore more accurate than RSPF, but DPSF files can be an order ofmagnitude larger than RSPF files for the same design. In addition,there is no specification for coupling caps in DSPF. DSPF is moresimilar to a SPICE netlist than the other formats.
|SPF||Standard ParasiticFormat (SPF). SPF is a Cadence DesignSystems standard for defining netlist parasitics. DSPF and RSPF are thetwo forms of SPF; the term SPF itself is sometimes used (or misused) torepresent parasitics in general. DSPF and RSPF both represent parasiticinformation as an RC network. |
|RSPF||Reduced StandardParasitic Format (RSPF). RSPF representseach net as an RC "pi" model, which consists of an equivalent”near" capacitance at the driver of the net, an equivalent"far"capacitance for the net, and an equivalent resistance connecting thesetwo capacitances. Each net has a single "pi" network for the network,regardless of how many pins are on the net. In addition to the pinetwork, RSPF causes the PrimeTime tool to calculate an Elmore delayfor every pin-to-pin interconnects delay.|
|SBPF||SBPF is a Synopsysbinary format supported by PrimeTime.Parasitic data converted to this format occupies less disk space andcan be read much faster than the same data stored in SPEF format. Youcan convert parasitics to SBPF, by reading them in and then writingthem out with the write_parasitics -format sbpf command.|
|DEF||Design Exchange Format(DEF) from Silicon IntegrationInitiative Inc. (Si2) and Cadence, customers will be able todownload for free from the OpenEDAWeb site. Both DEF and LEFbelong to physical design formats.|
|LEF||Library Exchange Format(LEF) from Silicon IntegrationInitiative Inc. (Si2) and Cadence, customers will be able to downloadfor free from the OpenEDA Web site.|
|SVRF||Standard VerificationRule Format (SVRF) This is theprogramming language for Mentor Graphics semiconductor physicalverification tools, like Calibre|
|RVE||Results ViewingEnvironment (RVE) is the interfaceand environment for checking the calibre output for drc andlvsresults .|
|MarketLandscape/ Product Definition||Howto undedrstand existing marketlandscape and to execute an excellent product definition/design||PDK101 Internal|
|DesignResources||AllIC design relatedresource||OPEN to public for feedbackand review.|
|SiliconTechnology and Foundry Fab Zone||Silicontechnologies fornow,will add III-V technology later on.||OPENtemporary to publicfor feedbackand review.|
|EDAZone||EDA/CAD/PDKinformation||OPEN to public for feedbackand review|
|Device andComponent||Allkind of high performance devices and component fromtechnologies and companies.||NOTyet online for now.|
|SPICE/MODEL||SPICEmodel for all kindof devices||OPENto public but underconstruction|
|IPfarm© 000960资金流向_短线技术指标Area||Allsort of soft andhard IP blocks for circuit design and IP developer information andentry page.||OPENto public but constantlyconstruction|
|ESD,Reliability,and Failure||ESD,reliability andfailure knowledge and case study||OPEN to public for feedbackand review|
|Product Test/Manufacture||Productmanufacturing,packaging, and testing information||NOTonline for now|
|Project Management||Allessential ideas and best practice for project management||PDK101 Internal|
|Marketing and Sale||Marketingand salerelated materials||PDK101 Internal|
|Cadsyntax example syntax exampleenceAssura||Official Cadence Web page|
|MixedSignal SOC design flow||Mentor Mixed signaldesign flow doc|
|CadenceTools Docs||Online Cadence tool pdffiles.|
|SynopsysNanosim doc||Online Synopsys Nanosimpdf files.|
|Demoon Demand||Online demo from serviceproviders|
|DeepChipEDA group||Online ESD discussiongroup. Lot of useful info.|
|OPENCORES||Open source IP repository|
|Design/IPReuse||Online Design reuse andIP service provider|
|AgilentOnline Demo||Online Agilent EDA demo|
|Xilinx designreuse document||Xilinx design resueDocument.|
|TechOnLine||many useful educationaltools for EE and IT|
|SiliconIntegration Initiative |
|Aorganization focuses on improvingproductivity and reducing cost in creating and producing integratedsilicon systems.|
|Openedaat SI2.org||OpenEDA.Si2.orgis a restrictedaccess site for the distribution of licensed materials from Si2development groups (councils, projects, boards, or workgroups).|
|OpenAccess||OpenAccessis a community effort to provide trueinteroperability, not just data exchange, among IC design tools throughan open standard data API and reference database supporting that APIfor IC design.|
|SoCCentral||SOCcentralbrings you the latest new about SOC/ASIC/FPGA design, EDA tools, designmethodologies, intellectual property (IP), and design reuse.|
|EDAboard||Online Analog IC designand layout discussion forum.|
|EEtimes||Online EEtimes website|
|Design-reuse||Design resue website.|
|ICDesign Quality Checklist||IC design quality ondesign magazine.|
|EDA Geek||EDA Geek publishes newsabout the electronic designautomation and semiconductor industry.|
|Cadence_CommunityForum||Cadence Community Forumfor Cadence tool users.|
|AlteraForum||A lot of good FPGA andEDA general information and discussion|
|LowPower Design||Low power design|
|eecatalog||some useful andinformative video clips about IC design and silicon technology.|
|low-powerwireless.com||Low power designspecific on wireless system.|
|CADFORUMS.COM||All AutoCad and Cadrelated discussion|
|Softpedia||An lot of GPL EDAsoftware codes and script for genericpurpos|